drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

230

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

63

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0x0000000c

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

230

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

252

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

254

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

422

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

915

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1933

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1983

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3654

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2713

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

91

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

91

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

87

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

91

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1445

#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc