drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

229

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

62

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

229

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

251

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

253

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

445

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

938

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1957

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2006

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3677

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2736

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

114

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

114

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

110

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

114

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1468

#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L