Symbol: UVD_CGC_CTRL__SYS_MODE__SHIFT
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h
238
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
61
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x00000010
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h
238
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h
260
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h
262
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
426
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
919
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h
1937
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h
1987
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h
3658
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h
2717
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h
95
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h
95
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h
91
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
95
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h
1449
#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10