drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

237

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

60

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

237

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

259

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

261

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

449

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

942

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1961

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2010

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3681

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2740

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

118

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

118

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

114

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

118

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1472

#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L