drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

266

#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

59

#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x0000001e

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

266

#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

288

#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

290

#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

440

#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

933

#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1951

#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e