drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

265

#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

58

#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

265

#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

287

#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

289

#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

463

#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

956

#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1975

#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L