drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

244

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

57

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x00000013

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

244

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

266

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

268

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

429

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

922

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1940

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1990

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3661

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2720

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

98

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

98

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

94

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

98

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1452

#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13