drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

243

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

56

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

243

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

265

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

267

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

452

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

945

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1964

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2013

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3684

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2743

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

121

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

121

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

117

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

121

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1475

#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L