drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

246

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

55

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x00000014

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

246

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

268

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

270

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

430

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

923

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1941

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1991

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3662

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2721

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

99

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

99

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

95

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

99

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1453

#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14