drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

245

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

54

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

245

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

267

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

269

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

453

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

946

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1965

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2014

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3685

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2744

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

122

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

122

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

118

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

122

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1476

#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L