drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

254

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

53

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x00000018

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

254

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

276

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

278

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

434

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

927

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1945

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1995

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3666

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2725

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

103

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

103

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

99

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

103

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1457

#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18