drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

253

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

52

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

253

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

275

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

277

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

457

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

950

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1969

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2018

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3689

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2748

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

126

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

126

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

122

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

126

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1480

#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L