drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

242

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

51

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x00000012

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

242

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

264

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

266

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

428

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

921

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1939

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1989

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3660

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2719

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

97

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

97

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

93

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

97

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1451

#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12