drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

241

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

50

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

241

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

263

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

265

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

451

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

944

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1963

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2012

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3683

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2742

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

120

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

120

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

116

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

120

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1474

#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L