drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1976

#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2024

#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3695

#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2754

#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

132

#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

132

#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

128

#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

132

#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1486

#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L