drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

255

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

48

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

255

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

277

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

279

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

458

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

951

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1970

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2019

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3690

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2749

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

127

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

127

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

123

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

127

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1481

#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L