drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1952

#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2001

#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3672

#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2731

#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

109

#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

109

#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

105

#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

109

#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1463

#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f