drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

259

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

46

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

259

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

281

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

283

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

460

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

953

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1972

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2021

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3692

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2751

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

129

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

129

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

125

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

129

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1483

#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L