drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

250

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

45

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x00000016

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

250

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

272

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

274

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

432

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

925

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1943

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1993

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3664

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2723

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

101

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

101

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

97

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

101

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1455

#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16