drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

249

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

44

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

249

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

271

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

273

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

455

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

948

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1967

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2016

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3687

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2746

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

124

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

124

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

120

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

124

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1478

#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L