drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

248

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

43

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x00000015

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

248

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

270

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

272

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

431

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

924

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1942

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1992

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3663

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2722

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

100

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

100

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

96

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

100

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1454

#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15