drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

247

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

42

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

247

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

269

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

271

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

454

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

947

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1966

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2015

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3686

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2745

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

123

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

123

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

119

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

123

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1477

#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L