drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

258

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

41

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x0000001a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

258

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

280

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

282

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

436

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

929

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1947

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1997

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3668

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2727

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

105

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

105

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

101

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

105

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1459

#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a