drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

257

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

40

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

257

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

279

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

281

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

459

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

952

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1971

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2020

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3691

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2750

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

128

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

128

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

124

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

128

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1482

#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L