Symbol: UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h
222
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
37
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x00000000
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h
222
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h
242
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h
244
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
418
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
911
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h
1929
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h
1979
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h
3650
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h
2709
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h
87
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h
87
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h
83
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
87
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h
1441
#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0