drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

252

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

39

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x00000017

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

252

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

274

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

276

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

433

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

926

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1944

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1994

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3665

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2724

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

102

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

102

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

98

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

102

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1456

#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17