drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

221

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

36

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

221

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

241

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

243

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

441

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

934

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1953

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2002

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3673

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2732

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

110

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

110

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

106

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

110

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1464

#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L