drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

225

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

34

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

225

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

247

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

249

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

443

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

936

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1955

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

2004

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3675

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2734

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

112

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

112

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

108

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

112

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1466

#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L