drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

224

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

33

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

224

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

246

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

248

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

419

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

912

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1930

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1980

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

3651

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2710

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

88

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

88

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

84

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

88

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

1442

#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2