Symbol: UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h
223
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h
32
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h
223
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h
245
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h
247
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
442
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
935
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h
1954
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h
2003
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h
3674
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h
2733
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h
111
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h
111
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h
107
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
111
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h
1465
#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL