drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

716

#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

31

#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

722

#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

896

#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

886

#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

4869

#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

7423

#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

10214

#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

7751

#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

6956

#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

64

#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2