drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

714

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

29

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

720

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

894

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

884

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

4868

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

7422

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

10213

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

7750

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

6955

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

63

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1