drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

713

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

28

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

719

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

893

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

883

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

4871

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

7425

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

10216

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

7753

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

6958

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

66

#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L