drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

712

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

27

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

718

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

892

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

882

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

4867

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

7421

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

10212

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

7749

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

6954

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

62

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0