drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_3_1_sh_mask.h

711

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h

26

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h

717

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h

891

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h

881

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

4870

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

7424

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

10215

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

7752

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

6957

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

65

#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L