SR
#define SR SPRG + 1
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(reg_name)\
#define SR(dispc, reg) \
#undef SR
#define SR(dss, reg) \
#undef SR
#define SR (10*RS) /* Shift register */
#define SR (10*RS) /* Shift register */
#define SR (10*RS) /* Shift register */
#define SR(off) (0x1400 + (off) * 8)
#define SR(n) ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x2c + (n) * 0x40) \
#define SR(reg) \
#undef SR
#define SR(reg) \
#undef SR
#define SR(r) \