drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

2621

#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

2469

#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

2427

#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

26057

#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

2822

#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

9011

#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x00000004

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

12402

#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

14272

#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

14670

#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4