drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

23837

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

22035

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

21526

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

23856

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

17495

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

28866

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

29443

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

16334

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

17639

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

17514

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

9763

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

19815

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7591

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x00000000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

8706

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

10308

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

10706

#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0