drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

8707

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

9018

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

7463

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

9010

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

4566

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

25034

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

25670

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

4459

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

3937

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

3843

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

24776

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000001FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

4785

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000001FFL

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

11087

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

12813

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

13211

#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff