drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

8702

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

9013

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

7458

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

9005

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

4561

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

25029

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

25665

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

4454

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

3932

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

3838

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

24771

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000001FFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

4780

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000001FFL

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

11085

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

12811

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

13209

#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff