drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

7779

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

8114

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

24673

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

27029

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

20734

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

32588

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

33129

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

2227

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

2075

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

2098

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

25528

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

2245

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

12656

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

14542

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

14940

#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10