drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

641

#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

606

#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

429

#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

447

#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

440

#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

409

#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h

632

#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h

921

#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h

920

#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h

943

#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h

937

#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1