drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

220

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

221

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

188

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

196

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

199

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

167

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h

960

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h

1044

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h

1062

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h

1568

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h

203

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h

512

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h

511

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h

518

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h

512

#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e