drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

222

#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

223

#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

190

#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

198

#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

201

#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

169

#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h

909

#define SDMA0_STATUS_REG__IDLE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h

989

#define SDMA0_STATUS_REG__IDLE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h

1007

#define SDMA0_STATUS_REG__IDLE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h

1513

#define SDMA0_STATUS_REG__IDLE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h

205

#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h

514

#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h

513

#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h

520

#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h

514

#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L