drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

1271

#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

1300

#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h

1160

#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h

1280

#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h

1728

#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h

2044

#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h

1283

#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h

1481

#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h

1287

#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h

1499

#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h

1489

#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1