Symbol: SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h
1060
#define SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h
1109
#define SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h
1076
#define SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h
1112
#define SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10