drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

321

#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

322

#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h

1019

#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h

1109

#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h

1129

#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h

1635

#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00

drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h

302

#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h

607

#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h

606

#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h

615

#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h

609

#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L