drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

317

#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

318

#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h

1018

#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h

1108

#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h

1128

#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h

1634

#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h

298

#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h

603

#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h

602

#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h

611

#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h

605

#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0