drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

319

#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

320

#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h

1022

#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h

1112

#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h

1132

#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h

1638

#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h

300

#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h

605

#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h

604

#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h

613

#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h

607

#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e