drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

311

#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

312

#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h

1014

#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h

1104

#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h

1124

#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h

1630

#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h

292

#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h

597

#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h

596

#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h

605

#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h

599

#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8